A reduced instruction set computer or RISC is a type of instruction set architecture used in the design of computer processors such as central processing units and graphics processing units. A key characteristic of RISC architecture is that it uses simpler instructions, operates at one instruction per cycle, and has a fixed instruction size. To compare, a complex instruction set computer or CISC architecture works by combining simple instructions into a single complex one, performing multiple operations per single operation.
Examples of CPUs and chipsets based on RISC include ARM-based processors such as the A Series and M Series chips from Apple, including the first-ever M1 processor, and Snapdragon processors from Qualcomm, PowerPC from the AIM Alliance, and SPARC from Oracle Corporation. Nonetheless, this article provides a simplified explanation of the characteristics, advantages, as well as disadvantages and limitations of RISC architecture and processor.
The Pros: Advantages and Characteristics of RISC
RISC processors perform difficult commands by merging them into simpler ones, while processors based on CISC architecture can perform multi-step operations or address modes within one instruction set. A more straightforward description of the difference between the two is that reduced instruction set computer tries to perform one thing only per instruction while complex instruction set computer tries to do more in a single instruction.
The following are the key advantages of reduced instruction set computer:
• It features a set of instructions that make it easier for compilers of high-level language to produce more efficient codes.
• A single instruction takes one cycle. Operation speed can be maximized without minimizing execution time.
• There is a fixed length of instruction, and the function uses only a few parameters, thus making instructions easier to pipeline.
• Another advantage of RISC is that it requires fewer instruction formats, a lesser number of instructions, and fewer addressing modes.
• The required number of transistors is lesser because the decoding logic is simple.
• Fewer transistors mean that more general-purpose registers and hardware can be fitted into the CPU or chipset.
• Having more registers allow a shorter time for loading from and storing values to the cache.
• From the side of manufacturing, less chip space is used due to the reduced instruction set. It also requires smaller components. These mean lower per-chip costs.
• RISC-based processors such as ARM processors are more energy-efficient and have lesser heat output compared to ones based on CISC.
The Cons: Disadvantages and Limitations of RISC
It is important to note that the differences between RISC and CISC define the major differences between ARM-based processors from ARM Ltd. such as those designed by Qualcomm and Apple and x86 processors from manufacturers such as Intel and AMD and
Below are the key disadvantages of reduced instruction set computer:
• The performance of a reduced instruction set computer processor depends on the capabilities of the compilers and programmers.
• Note that compilers also need to breakdown high-level instructions into many several simpler instructions.
• Translating a CISC code to RISC code increased the code size. The quality of the code will depend on both the compiler and the instruction set of the machine.
• Another drawback is that developers need to exert more effort when compared to developing for CISC processors.
• The resulting processors require large memory caches. There is a need to use high-speed memory systems to feed instructions.
• Note that the full capabilities, features, and advantages of RISC remain dependent on the specific architecture.
FURTHER READINGS AND REFERENCES
- Ibrahim, D. 2015. “Microcomputer Systems.” In PIC32 Microcontrollers and the Digilent ChipKIT. Elsevier. DOI: 1016/b978-0-08-099934-0.00001-6
- Koo, K., Rho, G. S., Kwon, W. H., Park, J., and Chang, N. 1998. Architectural Design of an RISC Processor for Programmable Logic Controllers. Journal of Systems Architecture. 44(5): 311-325. DOI: 1016/s1383-7621(97)00011-8
- Stallings, W. 1988. “Reduced Instruction Set Computer Architecture. Proceedings of the IEEE. 76(1): 38-55. DOI: 1109/5.3287